In a typical computer system, some components are coupled to a device of a chipset via serial buses. The chipset acts as an interface between the components and a processor. As the processor speed increases, the speed of the serial interfaces of the chipset devices has to increase in order to keep up with the processor speed. The speed of a serial interface is typically several times of the speed of the processor.
With the advent of high-speed serial interface, the design of the interface has become increasingly complicated, and therefore, a more sophisticated and robust testing technique is necessary to test the interface. The conventional method of measuring signals using an external tester is inadequate for fully testing a high-speed serial interface because the speed of legacy testers is limited. Furthermore, the limited number of tester channels in the legacy testers poses another problem in testing the chipset device because there may not be enough tester channels to test every pin of the chipset device as the complexity of the chipset device increases. Because of the limited number of tester channels and the high-speed tests, the transmitter and the receiver of the device are connected on a load board during some high-speed data transfer tests. However, it is still difficult to test for leakage at the pins and/or other parts of the device with the limited number of tester channels.
Alternatively, some semiconductor manufacturers replace the legacy testers with high-speed testers in order to provide more tester channels and to speed up the measurement of small signals during testing. However, replacing the legacy testers with the high-speed testers significantly increases the cost of manufacturing chipset devices with high-speed serial interface because the high-speed testers are very expensive.